The processing element of the VX/2

Each PE consists of

• a scalar unit (SU)
  • a long-instruction-word (LIW) RISC CPU
  • approximately 100 MFlop/s peak
  • up to three operations simultaneously in a single clock cycle.
• a vector unit (VU)
  • 1 load, 1 store, 1 add and 1 multiply pipe, each completing 8 operations per cycle.The divide pipe does 8 operations per 7 cycles.
  • chained load-mult-add allowing a peak of 2.2 GFlop/s.
  • 128 kB of vector registers.
• memory (MSU)
  • 2 GB of SDRAM memory.
• and a data transfer unit (DTU)
  • giving direct memory access data communication to the high speed Crossbar Network